Hardware and software Co-design

The course covers the design and development aspects of heterogeneous (hardware/software) digital systems. This course explores the process involved in defining system specification and how design space exploration can be done. Special focus is given on design quality and cost estimation, partitioning source description into different implementation domains, target code generation, interface synthesis and co-verification.

Topic 1: Introduction to hardware and software co-design

Introduction to System-on-chip

HW/SW Co-design

Platform based design frameworks

SoC design on Intel FPGAs

SoC design on Xilinx FPGAs

Topic 2: System Verilog Fundamentals

Upgrading from Verilog to System Verilog

Data declaration

Variables definition

Operators and expressions

Constructs for design intent

Parameterization

Modelling memories

Topic 3: System Verilog Testbench and Interface Constructs

System Verilog testbench

Self-checking testbench

Testbench with test vectors

System Verilog interface construct

Design using interface construct

Topic 4: System Verilog DPI-C and HW/SW Co-Simulation

HW/SW co-simulation models

System Verilog enhancements of task and function

Modelling with System Verilog DPI-C

Untimed functional (UTF) co-simulation modelling

HW/SW testbench, UTF co-simulation

Topic 5: Introduction to Digital Design Optimization

RTL and HLS design flows

Design alternatives for optimizations

Loop unrolling in mapping of iterative algorithm

Flow graph model for performance estimation

Mapping arrays to memory block

Topic 6: Optimizing RTL Design for Area and Latency

Area optimization with serial processing

Latency optimization with datapath

Designs with concurrent-serial processing datapath

Topic 7: Optimizing RTL Design through Pipelining

Pipelining definition and concepts

Measuring performance in pipelined architecture

Task pipelining

Loop pipelining

Topic 8: Case study of RTL design optimizations

SAD algorithm and functional unit

Dot-product computation unit

Matrix multiplication unit

Topic 9: C-based High-level Synthesis

Basics of C-synthesis program

Default behavior and baseline implementation

Default interface synthesis

C-testbench and C/RTL co-simulation

Topic 10: Design optimization for C-based HLS

Summary of optimization directives

Array mapping optimization

Loop optimization

Controlling the hardware cores

Writing HLS codes

Design considerations and guidelines

Topic 11: HLS case studies

Dot-product computation unit

FIR digital filter

Matrix multiplication

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