Hardware and software Co-design

The course covers the design and development aspects of heterogeneous (hardware/software) digital systems. This course explores the process involved in defining system specification and how design space exploration can be done. Special focus is given on design quality and cost estimation, partitioning source description into different implementation domains, target code generation, interface synthesis and co-verification.

Topic 2: System Verilog Fundamentals

Upgrading from Verilog to System Verilog

Data declaration

Variables definition

Operators and expressions

Constructs for design intent

Modelling FSM

Parameterization

Modelling memories

Topic 4: System Verilog DPI-C and HW/SW Co-Simulation

HW/SW co-simulation models

System Verilog enhancements of task and function

Modelling with System Verilog DPI-C

Untimed functional (UTF) co-simulation modelling

HW/SW testbench, UTF co-simulation

Topic 6: Optimizing RTL Design for Area and Latency

Area optimization with serial processing

Latency optimization with datapath

Designs with concurrent-serial processing datapath

Topic 8: Case study of RTL design optimizations

SAD algorithm and functional unit

Dot-product computation unit

Matrix multiplication unit

Topic 10: Design optimization for C-based HLS

Summary of optimization directives

Array mapping optimization

Loop optimization

Controlling the hardware cores

Writing HLS codes

Design considerations and guidelines