VLSI Circuits and Design
Topic-1: Introduction
ENIAC - The first electronic computer (1946)
Intel Pentium (IV) microprocessor
Moore’s law in Microprocessors
Topic-2: MOS Transistor
The NMOS Transistor Cross Section
Switch Model of NMOS Transistor
Switch Model of PMOS Transistor
The Body Effect (for NMOS transistor)
Voltage-Current Relation: Linear Mode
Voltage-Current Relation: Saturation Mode
Voltage-Current Relation: Velocity Saturation
The Unified MOS Current-Source Model
Transistor as a Switch – Equivalent Resistance
The Transistor Modeled as a Switch
Average Distribution of Channel Capacitance
Topic-3: CMOS Inverter
Mapping Logic Levels to the Voltage Domain
CMOS Inverter Load Lines
CMOS Inverter VTC
Switch Model of Dynamic Behavior
Relative Transistor Sizing
Switching Threshold
Switch Threshold Example
Noise Margins: Determining VIH and VIL
CMOS Inverter VTC from Simulation
Gain Determinates
Impact of Process Variation on VTC Curve
Scaling the Supply Voltage
Delay Definitions
The Miller Effect
Extrinsic (Fan-Out) Capacitance
Layout of Two Chained Inverters
Components of CL
Inverter Propagation Delay
Inverter Transient Response
Design for Performance
NMOS/PMOS Ratio
PMOS/NMOS Ratio Effects
Device Sizing for Performance
Sizing Impacts on Delay
Impact of Fanout on Delay
Inverter Chain
Sizing the Inverters in the Chain
Determining N: Optimal Number of Inverters
Optimum Effective Fan-Out
Example of Inverter (Buffer) Staging
Impact of Buffer Staging for Large CL
Input Signal Rise/Fall Time
Delay with Long Interconnects
Topic-4: Combinational Logic
Combinational vs. Sequential Logic
Static CMOS Circuit
Transistors .in Series/Parallel Connection
Threshold Drops
Complementary CMOS Logic Style
Constructing a Complex Gate
Cell Design
Standard Cell Layout Methodology
Stick Diagrams
Consistent Euler Path
Multi-Fingered Transistors
CMOS Properties
Switch Delay Model
Input Pattern Effects on Delay
Transistor Sizing
Fan-In Considerations
Design Techniques
Sizing Logic Paths for Speed
Buffer Example
Logical Effort
Delay in a Logic Gate
Branching Effort
Multistage Networks
Optimum Effort per Stage
Optimal Number of Stages
Ratioed Logic
Active Loads
Pseudo-NMOS
Improved Loads
DCVSL Example
Pass-Transistor Logic
NMOS-Only Logic
Level Restoring Transistor
Restorer Sizing
Complementary Pass Transistor Logic
Transmission Gate
Resistance of Transmission Gate
Pass-Transistor Based Multiplexer
Delay in Transmission Gate Networks
Delay Optimization
Dynamic Logic
Properties of Dynamic Gates
Charge Leakage
Backgate Coupling
Clock Feedthrough
Cascading Dynamic Gates
Domino Logic
Footless Domino
NORA Logic
Topic-5: Logical effort
Design Technique Using Logical Effort
Intrinsic Delay Term
Logical Effort Term
Delay as a Function of Fan-Out
Path Delay Equation Derivation
Gate Sizes
Decoder Example
Limits of Logical Effort
Topic-6: Power
Why Power Matters
Power and Energy Figures of Merit
Power versus Energy
Power in Circuit Elements
Charging a Capacitor
Switching Waveforms
PDP and EDP
CMOS Energy & Power Equations
Power Dissipation Sources
Switching Power Consumption
Lowering Switching Power
Short Circuit Power Consumption
Short Circuit Current Determinants
Impact of CL on Psc
Ipeak as a Function of CL
Psc as a Function of Rise/Fall Times
Switching Power Reduction
Clock Gating
Capacitance
Voltage/Frequency
Static Power
Leakage (Static) Power Consumption
Leakage as a Function of VT
TSMC Processes Leakage and VT
Exponential Increase in Leakage Currents
Leakage Control
Gate Leakage
Junction Leakage
Power Gating
Review: Energy & Power Equations
Switching Power as a Function of Device Size
Switching Power Consumption is Data Dependent
NOR Gate Transition Probabilities