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Topic 5b: MOSFET DC Voltage Divider Bias
Topic 6a: Op-Amp Linear Applications
Inverting amplifier
Non-inverting amplifier
Voltage follower
Difference amplifier
Inverting summer amplifier
Non-inverting summer amplifier
Topic 6b: Op-Amp Non-Linear Applications
Quartus II tutorial
VLSI design automation
Digital Electronic
Analog and Digital Systems
Analog Quantities
Basic Logic Functions
Basic System Functions
Binary Digits and Logic Levels
Digital Waveforms
Integrated Circuits
Periodic Pulse Waveforms
Programmable Logic
Pulse Definitions
Pulse Definitions
Serial and Parallel Data
Test and Measurement Instruments
Timing Diagrams
VLSI Circuits and Design
Average Distribution of Channel Capacitance
Challenges in Digital Design
Cost of Integrated Circuits
Cost per Transistor
Current Determinates
Design Abstraction Levels
Design Metrics
Die Cost
Die Size Growth
Drain-Bulk Capacitance: Keq
ENIAC - The first electronic computer (1946)
Evolution in Complexity
Frequency
Intel 4004 Micro-Processor
Intel Pentium (IV) microprocessor
Long-Channel I-V Plot (NMOS)
Moore’s Law
Moore’s law in Microprocessors
MOS Capacitance Model
MOS Channel Capacitances
MOS Diffusion Capacitances
MOS ID-VGS Characteristics
MOS Intrinsic Capacitances
MOS Overlap Capacitances
Not Only Microprocessors
Power density
Power Dissipation
Power will be a major problem
Productivity Trends
Review: Reverse Bias Diode
Short Channel I-V Plot (NMOS)
Short Channel I-V Plot (PMOS)
Short-Channel Effects
Source Junction View
Sources of Capacitance
Subthreshold Conductance
Switch Model of NMOS Transistor
Switch Model of PMOS Transitor
The Body Effect (for NMOS transistor)
The First Computer
The First Integrated Circuits
The MOS Transistor
The NMOS Transistor Cross Section
The Threshold Voltage
The Transistor Modeled as a Switch
The Transistor Revolution
The Unified MOS Current-Source Model
Threshold Voltage concepts
Transistor as a Switch – Equivalent Resistance
Transistor Capacitance Values
Transistor Counts
Transistor in Linear Mode
Transistor in Saturation Mode
Velocity Saturation Effects
Voltage-Current Relation: Linear Mode
Voltage-Current Relation: Saturation Mode
Voltage-Current Relation: Velocity Saturation
Why Scaling?
DC Operation
Yield
Noise Margins
The Ideal Inverter
Mapping Logic Levels to the Voltage Domain
Steady State Response
CMOS Properties
CMOS Inverter Load Lines
CMOS Inverter VTC
Switch Model of Dynamic Behavior
Relative Transistor Sizing
Switching Threshold
Switch Threshold Example
Noise Margins: Determining VIH and VIL
CMOS Inverter VTC from Simulation
Gain Determinates
Impact of Process Variation on VTC Curve
Scaling the Supply Voltage
Delay Definitions
The Miller Effect
Extrinsic (Fan-Out) Capacitance
Layout of Two Chained Inverters
Components of CL
Inverter Propagation Delay
Inverter Transient Response
Design for Performance
NMOS/PMOS Ratio
PMOS/NMOS Ratio Effects
Device Sizing for Performance
Sizing Impacts on Delay
Impact of Fanout on Delay
Inverter Chain
Sizing the Inverters in the Chain
Determining N: Optimal Number of
Inverters
Optimum Effective Fan-Out
Example of Inverter (Buffer) Staging
Impact of Buffer Staging for Large CL
Input Signal Rise/Fall Time
Delay with Long Interconnects
Fan-In Considerations
Design Techniques
Sizing Logic Paths for Speed
Buffer Example
Logical Effort
Delay in a Logic Gate
Branching Effort
Multistage Networks
Optimum Effort per Stage
Optimal Number of Stages
Ratioed Logic
Active Loads
Pseudo-NMOS
Improved Loads
DCVSL Example
Pass-Transistor Logic
NMOS-Only Logic
Level Restoring Transistor
Restorer Sizing
Complementary Pass Transistor Logic
Transmission Gate
Resistance of Transmission Gate
Pass-Transistor Based Multiplexer
Delay in Transmission Gate Networks
Delay Optimization
Dynamic Logic
Properties of Dynamic Gates
Charge Leakage
Backgate Coupling
Clock Feedthrough
Cascading Dynamic Gates
Domino Logic
Footless Domino
NORA Logic
Design Technique Using Logical Effort
Intrinsic Delay Term
Logical Effort Term
Delay as a Function of Fan-Out
Path Delay Equation Derivation
Gate Sizes
Decoder Example
Limits of Logical Effort
Why Power Matters
Power and Energy Figures of Merit
Power versus Energy
Power in Circuit Elements
Charging a Capacitor
Switching Waveforms
PDP and EDP
CMOS Energy & Power Equations
Power Dissipation Sources
Switching Power Consumption
Lowering Switching Power
Short Circuit Power Consumption
Short Circuit Current Determinants
Impact of CL on Psc
Ipeak as a Function of CL
Psc as a Function of Rise/Fall Times
Switching Power Reduction
Clock Gating
Capacitance
VoltageFrequency
Static Power
Leakage (Static) Power Consumption
Leakage as a Function of VT
TSMC Processes Leakage and VT
Exponential Increase in Leakage Currents
Leakage Control
Gate Leakage
Junction Leakage
Power Gating
Review: Energy & Power Equations
Switching Power as a Function of Device Size
Switching Power Consumption is Data Dependent
NOR Gate Transition Probabilities
HWSWCodesign
Modelling memories
Parameterization
SoC design on Xilinx FPGAs
SoC design on Intel FPGAs
Platform based design frameworks
Introduction to System-on-chip
FPGA-based SoC
HWSW Co-design
Upgrading from Verilog to System Verilog
Variables definition
Operators and expressions
Constructs for design intent
Modelling FSM
System Verilog testbench
Self-checking testbench
Testbench with test vectors
System Verilog interface construct
Design using interface construct
HW/SW co-simulation models
System Verilog enhancements of task and function
Untimed functional (UTF) co-simulation modelling
HW/SW testbench, UTF co-simulation
Design alternatives for optimizations
RTL and HLS design flows
Modelling with System Verilog DPI-C
Loop unrolling in mapping of iterative algorithm
Flow graph model for performance estimation
Mapping arrays to memory block
Area optimization with serial processing
Latency optimization with datapath
Designs with concurrent-serial processing datapath
Pipelining definition and concepts
Measuring performance in pipelined architecture
Task pipelining
Loop pipelining
SAD algorithm and functional unit
Dot-product computation unit
Matrix multiplication unit
Basics of C-synthesis program
Default behavior and baseline implementation
Default interface synthesis
C-testbench and C/RTL co-simulation
Summary of optimization directives
Array mapping optimization
Loop optimization
Controlling the hardware cores
Writing HLS codes
Design considerations and guidelines
Dot-product computation unit
FIR digital filter
Matrix multiplication
Sobel filter
Links
Activities 2020
2020-01-01
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2020-07-25
2020-07-26
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2020-07-28
2020-07-29
2020-07-30
2020-07-31
Activities 2021
Profile
Background
Education
Publications
Research Interests
Students
Past students
Courses
Digital VLSI system
Electronics
Topic 5b: MOSFET DC Voltage Divider Bias
Topic 6a: Op-Amp Linear Applications
Inverting amplifier
Non-inverting amplifier
Voltage follower
Difference amplifier
Inverting summer amplifier
Non-inverting summer amplifier
Topic 6b: Op-Amp Non-Linear Applications
Quartus II tutorial
VLSI design automation
Digital Electronic
Analog and Digital Systems
Analog Quantities
Basic Logic Functions
Basic System Functions
Binary Digits and Logic Levels
Digital Waveforms
Integrated Circuits
Periodic Pulse Waveforms
Programmable Logic
Pulse Definitions
Pulse Definitions
Serial and Parallel Data
Test and Measurement Instruments
Timing Diagrams
VLSI Circuits and Design
Average Distribution of Channel Capacitance
Challenges in Digital Design
Cost of Integrated Circuits
Cost per Transistor
Current Determinates
Design Abstraction Levels
Design Metrics
Die Cost
Die Size Growth
Drain-Bulk Capacitance: Keq
ENIAC - The first electronic computer (1946)
Evolution in Complexity
Frequency
Intel 4004 Micro-Processor
Intel Pentium (IV) microprocessor
Long-Channel I-V Plot (NMOS)
Moore’s Law
Moore’s law in Microprocessors
MOS Capacitance Model
MOS Channel Capacitances
MOS Diffusion Capacitances
MOS ID-VGS Characteristics
MOS Intrinsic Capacitances
MOS Overlap Capacitances
Not Only Microprocessors
Power density
Power Dissipation
Power will be a major problem
Productivity Trends
Review: Reverse Bias Diode
Short Channel I-V Plot (NMOS)
Short Channel I-V Plot (PMOS)
Short-Channel Effects
Source Junction View
Sources of Capacitance
Subthreshold Conductance
Switch Model of NMOS Transistor
Switch Model of PMOS Transitor
The Body Effect (for NMOS transistor)
The First Computer
The First Integrated Circuits
The MOS Transistor
The NMOS Transistor Cross Section
The Threshold Voltage
The Transistor Modeled as a Switch
The Transistor Revolution
The Unified MOS Current-Source Model
Threshold Voltage concepts
Transistor as a Switch – Equivalent Resistance
Transistor Capacitance Values
Transistor Counts
Transistor in Linear Mode
Transistor in Saturation Mode
Velocity Saturation Effects
Voltage-Current Relation: Linear Mode
Voltage-Current Relation: Saturation Mode
Voltage-Current Relation: Velocity Saturation
Why Scaling?
DC Operation
Yield
Noise Margins
The Ideal Inverter
Mapping Logic Levels to the Voltage Domain
Steady State Response
CMOS Properties
CMOS Inverter Load Lines
CMOS Inverter VTC
Switch Model of Dynamic Behavior
Relative Transistor Sizing
Switching Threshold
Switch Threshold Example
Noise Margins: Determining VIH and VIL
CMOS Inverter VTC from Simulation
Gain Determinates
Impact of Process Variation on VTC Curve
Scaling the Supply Voltage
Delay Definitions
The Miller Effect
Extrinsic (Fan-Out) Capacitance
Layout of Two Chained Inverters
Components of CL
Inverter Propagation Delay
Inverter Transient Response
Design for Performance
NMOS/PMOS Ratio
PMOS/NMOS Ratio Effects
Device Sizing for Performance
Sizing Impacts on Delay
Impact of Fanout on Delay
Inverter Chain
Sizing the Inverters in the Chain
Determining N: Optimal Number of
Inverters
Optimum Effective Fan-Out
Example of Inverter (Buffer) Staging
Impact of Buffer Staging for Large CL
Input Signal Rise/Fall Time
Delay with Long Interconnects
Fan-In Considerations
Design Techniques
Sizing Logic Paths for Speed
Buffer Example
Logical Effort
Delay in a Logic Gate
Branching Effort
Multistage Networks
Optimum Effort per Stage
Optimal Number of Stages
Ratioed Logic
Active Loads
Pseudo-NMOS
Improved Loads
DCVSL Example
Pass-Transistor Logic
NMOS-Only Logic
Level Restoring Transistor
Restorer Sizing
Complementary Pass Transistor Logic
Transmission Gate
Resistance of Transmission Gate
Pass-Transistor Based Multiplexer
Delay in Transmission Gate Networks
Delay Optimization
Dynamic Logic
Properties of Dynamic Gates
Charge Leakage
Backgate Coupling
Clock Feedthrough
Cascading Dynamic Gates
Domino Logic
Footless Domino
NORA Logic
Design Technique Using Logical Effort
Intrinsic Delay Term
Logical Effort Term
Delay as a Function of Fan-Out
Path Delay Equation Derivation
Gate Sizes
Decoder Example
Limits of Logical Effort
Why Power Matters
Power and Energy Figures of Merit
Power versus Energy
Power in Circuit Elements
Charging a Capacitor
Switching Waveforms
PDP and EDP
CMOS Energy & Power Equations
Power Dissipation Sources
Switching Power Consumption
Lowering Switching Power
Short Circuit Power Consumption
Short Circuit Current Determinants
Impact of CL on Psc
Ipeak as a Function of CL
Psc as a Function of Rise/Fall Times
Switching Power Reduction
Clock Gating
Capacitance
VoltageFrequency
Static Power
Leakage (Static) Power Consumption
Leakage as a Function of VT
TSMC Processes Leakage and VT
Exponential Increase in Leakage Currents
Leakage Control
Gate Leakage
Junction Leakage
Power Gating
Review: Energy & Power Equations
Switching Power as a Function of Device Size
Switching Power Consumption is Data Dependent
NOR Gate Transition Probabilities
HWSWCodesign
Modelling memories
Parameterization
SoC design on Xilinx FPGAs
SoC design on Intel FPGAs
Platform based design frameworks
Introduction to System-on-chip
FPGA-based SoC
HWSW Co-design
Upgrading from Verilog to System Verilog
Variables definition
Operators and expressions
Constructs for design intent
Modelling FSM
System Verilog testbench
Self-checking testbench
Testbench with test vectors
System Verilog interface construct
Design using interface construct
HW/SW co-simulation models
System Verilog enhancements of task and function
Untimed functional (UTF) co-simulation modelling
HW/SW testbench, UTF co-simulation
Design alternatives for optimizations
RTL and HLS design flows
Modelling with System Verilog DPI-C
Loop unrolling in mapping of iterative algorithm
Flow graph model for performance estimation
Mapping arrays to memory block
Area optimization with serial processing
Latency optimization with datapath
Designs with concurrent-serial processing datapath
Pipelining definition and concepts
Measuring performance in pipelined architecture
Task pipelining
Loop pipelining
SAD algorithm and functional unit
Dot-product computation unit
Matrix multiplication unit
Basics of C-synthesis program
Default behavior and baseline implementation
Default interface synthesis
C-testbench and C/RTL co-simulation
Summary of optimization directives
Array mapping optimization
Loop optimization
Controlling the hardware cores
Writing HLS codes
Design considerations and guidelines
Dot-product computation unit
FIR digital filter
Matrix multiplication
Sobel filter
Links
Activities 2020
2020-01-01
2020-01-01
2020-01-02
2020-01-03
2020-01-04
2020-01-05
2020-01-05
2020-01-05
2020-01-06
2020-01-07
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2020-07-23
2020-07-24
2020-07-25
2020-07-26
2020-07-27
2020-07-28
2020-07-29
2020-07-30
2020-07-31
Activities 2021
More
Profile
Background
Education
Publications
Research Interests
Students
Past students
Courses
Digital VLSI system
Electronics
Topic 5b: MOSFET DC Voltage Divider Bias
Topic 6a: Op-Amp Linear Applications
Inverting amplifier
Non-inverting amplifier
Voltage follower
Difference amplifier
Inverting summer amplifier
Non-inverting summer amplifier
Topic 6b: Op-Amp Non-Linear Applications
Quartus II tutorial
VLSI design automation
Digital Electronic
Analog and Digital Systems
Analog Quantities
Basic Logic Functions
Basic System Functions
Binary Digits and Logic Levels
Digital Waveforms
Integrated Circuits
Periodic Pulse Waveforms
Programmable Logic
Pulse Definitions
Pulse Definitions
Serial and Parallel Data
Test and Measurement Instruments
Timing Diagrams
VLSI Circuits and Design
Average Distribution of Channel Capacitance
Challenges in Digital Design
Cost of Integrated Circuits
Cost per Transistor
Current Determinates
Design Abstraction Levels
Design Metrics
Die Cost
Die Size Growth
Drain-Bulk Capacitance: Keq
ENIAC - The first electronic computer (1946)
Evolution in Complexity
Frequency
Intel 4004 Micro-Processor
Intel Pentium (IV) microprocessor
Long-Channel I-V Plot (NMOS)
Moore’s Law
Moore’s law in Microprocessors
MOS Capacitance Model
MOS Channel Capacitances
MOS Diffusion Capacitances
MOS ID-VGS Characteristics
MOS Intrinsic Capacitances
MOS Overlap Capacitances
Not Only Microprocessors
Power density
Power Dissipation
Power will be a major problem
Productivity Trends
Review: Reverse Bias Diode
Short Channel I-V Plot (NMOS)
Short Channel I-V Plot (PMOS)
Short-Channel Effects
Source Junction View
Sources of Capacitance
Subthreshold Conductance
Switch Model of NMOS Transistor
Switch Model of PMOS Transitor
The Body Effect (for NMOS transistor)
The First Computer
The First Integrated Circuits
The MOS Transistor
The NMOS Transistor Cross Section
The Threshold Voltage
The Transistor Modeled as a Switch
The Transistor Revolution
The Unified MOS Current-Source Model
Threshold Voltage concepts
Transistor as a Switch – Equivalent Resistance
Transistor Capacitance Values
Transistor Counts
Transistor in Linear Mode
Transistor in Saturation Mode
Velocity Saturation Effects
Voltage-Current Relation: Linear Mode
Voltage-Current Relation: Saturation Mode
Voltage-Current Relation: Velocity Saturation
Why Scaling?
DC Operation
Yield
Noise Margins
The Ideal Inverter
Mapping Logic Levels to the Voltage Domain
Steady State Response
CMOS Properties
CMOS Inverter Load Lines
CMOS Inverter VTC
Switch Model of Dynamic Behavior
Relative Transistor Sizing
Switching Threshold
Switch Threshold Example
Noise Margins: Determining VIH and VIL
CMOS Inverter VTC from Simulation
Gain Determinates
Impact of Process Variation on VTC Curve
Scaling the Supply Voltage
Delay Definitions
The Miller Effect
Extrinsic (Fan-Out) Capacitance
Layout of Two Chained Inverters
Components of CL
Inverter Propagation Delay
Inverter Transient Response
Design for Performance
NMOS/PMOS Ratio
PMOS/NMOS Ratio Effects
Device Sizing for Performance
Sizing Impacts on Delay
Impact of Fanout on Delay
Inverter Chain
Sizing the Inverters in the Chain
Determining N: Optimal Number of
Inverters
Optimum Effective Fan-Out
Example of Inverter (Buffer) Staging
Impact of Buffer Staging for Large CL
Input Signal Rise/Fall Time
Delay with Long Interconnects
Fan-In Considerations
Design Techniques
Sizing Logic Paths for Speed
Buffer Example
Logical Effort
Delay in a Logic Gate
Branching Effort
Multistage Networks
Optimum Effort per Stage
Optimal Number of Stages
Ratioed Logic
Active Loads
Pseudo-NMOS
Improved Loads
DCVSL Example
Pass-Transistor Logic
NMOS-Only Logic
Level Restoring Transistor
Restorer Sizing
Complementary Pass Transistor Logic
Transmission Gate
Resistance of Transmission Gate
Pass-Transistor Based Multiplexer
Delay in Transmission Gate Networks
Delay Optimization
Dynamic Logic
Properties of Dynamic Gates
Charge Leakage
Backgate Coupling
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Design Technique Using Logical Effort
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Why Power Matters
Power and Energy Figures of Merit
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Power Dissipation Sources
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Ipeak as a Function of CL
Psc as a Function of Rise/Fall Times
Switching Power Reduction
Clock Gating
Capacitance
VoltageFrequency
Static Power
Leakage (Static) Power Consumption
Leakage as a Function of VT
TSMC Processes Leakage and VT
Exponential Increase in Leakage Currents
Leakage Control
Gate Leakage
Junction Leakage
Power Gating
Review: Energy & Power Equations
Switching Power as a Function of Device Size
Switching Power Consumption is Data Dependent
NOR Gate Transition Probabilities
HWSWCodesign
Modelling memories
Parameterization
SoC design on Xilinx FPGAs
SoC design on Intel FPGAs
Platform based design frameworks
Introduction to System-on-chip
FPGA-based SoC
HWSW Co-design
Upgrading from Verilog to System Verilog
Variables definition
Operators and expressions
Constructs for design intent
Modelling FSM
System Verilog testbench
Self-checking testbench
Testbench with test vectors
System Verilog interface construct
Design using interface construct
HW/SW co-simulation models
System Verilog enhancements of task and function
Untimed functional (UTF) co-simulation modelling
HW/SW testbench, UTF co-simulation
Design alternatives for optimizations
RTL and HLS design flows
Modelling with System Verilog DPI-C
Loop unrolling in mapping of iterative algorithm
Flow graph model for performance estimation
Mapping arrays to memory block
Area optimization with serial processing
Latency optimization with datapath
Designs with concurrent-serial processing datapath
Pipelining definition and concepts
Measuring performance in pipelined architecture
Task pipelining
Loop pipelining
SAD algorithm and functional unit
Dot-product computation unit
Matrix multiplication unit
Basics of C-synthesis program
Default behavior and baseline implementation
Default interface synthesis
C-testbench and C/RTL co-simulation
Summary of optimization directives
Array mapping optimization
Loop optimization
Controlling the hardware cores
Writing HLS codes
Design considerations and guidelines
Dot-product computation unit
FIR digital filter
Matrix multiplication
Sobel filter
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